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ISL5239
General Comments About Modes
Once a trigger is detected in the ARMED condition, all
following triggers are ignored during the sequence. The
system does not acknowledge new triggers until a new
transaction is invoked and re-armed. When a new mode is
invoked, all subsequent invocations of new modes during the
duration of its sequence is ignored, except in the loop mode.
In the loop mode, an input memory mode change to IDLE is
processed immediately.
When in the IDLE, all controls, addresses, and data, default
to the processor interface values.
Triggers
When a capture memory is ARMED, i.e. waiting for a trigger
to happen, the activation of the trigger occurs in three ways
— external, data dependent, and user invoked. The trigger
select, 0x04, bits 5:4, provides the selection of the trigger
source. When the pre-distorter magnitude bus values fall
between the range of 0x09 minimum and 0x0a maximum,
the data dependent trigger activates. The first of these
transitions causes a trigger to be detected and the remaining
triggers during the capture sequence is ignored.
To invoke the user invoked trigger, 0x04, 5:4, set to
processor, the programmer writes a TRIGGER to the 0x04,
bit 6 processor trigger register. After a TRIGGER is in the
field, the user initiates the trigger by just writing to that
register. The user does not have to reset the trigger back to
IDLE. By setting the processor trigger bit to IDLE when not in
use, it keeps the circuit quiet and allows the user to write to
other values at that address without causing a trigger to
occur during operation. To disable the processor trigger, the
user should change trigger select to something other than
PROCESSOR and then change values in processor trigger.
If trigger select is not set to PROCESSOR, the system
ignores the trigger generated by processor trigger.
The feedback and input memory circuit uses the same
trigger; both circuits trigger at the same point with its
operation registers causing different operations to occur. The
user should monitor input memory status and feedback
memory status simultaneously before activating triggers.
Make sure both status registers are in ARMED before
activating triggers or the results from the capture can be
erroneous and data can be overwritten. Selecting processor
trigger (register 0x04, bits 5:4 = 00) while arming the input
and feedback memory circuits is a convenient way to ensure
no unexpected triggers occur before confirming ARMED
status of both circuits.
Input Data to Input Memory
There are three sources of input data to the input memory —
interpolator, pre-distorter’s data outputs, and the pre-
distorter’s magnitude. Data from the interpolator and the
predistort output are the upper 16 bits with or without
rounding. Only 16 of the original 20 bits of I or Q is loaded
12
into the memory. The I data is read from the memory on the
DataHigh register and the Q data, DataLow register.
In the predistort magnitude input, the data is unsigned 16
bits and the software has to reshuffle the data to extract the
original magnitude. The DataHigh contains only the pre-
distorter magnitude bit 15, and the DataLow contains the
pre-distorter magnitude 14:0.
Writing/Reading the Memories from the Processor
Interface
In the auto-increment mode, the data is loaded in 16-bit
increments. The low word is written or read first followed by
the high word. The high word increments the address
counter and generates the actual write to the memory. For
reading, it just increments the counter. The input memory
select 0x04, bit 12, selects the memory to be written to or
read from.
When writing or reading a specific address, the 0x0b
address register must be loaded before the 0x0c and 0x0d
memory data registers. In the write, the high word
transaction will trigger the actual write to the memory and a
low word must be written first. For additional details, see the
uP interface section.
Microprocessor Interface
The microprocessor interface allows the ISL5239 to appear
as a memory mapped peripheral to the μ P. All registers can
be accessed through this interface. The interface consists of
a 16 bit bidirectional data bus, P<15:0>, six bit address bus,
A<5:0>, a write strobe (WR), a read strobe (RD) and a chip
enable (CE). The interface is configured for separate read
and write strobe inputs.
The processor interface provides a simple parallel
Data/Control/Address bus for monitoring and controlling its
operation. The processor interface is asynchronous to the
CLK, and BUSY signal is included to indicate when read and
write operations are complete.
The register configuration is master/slave, where the slave
registers are updated from the masters and all reads access
the slaves.
The master registers are clocked by the μ P WR strobe, are
writable and cleared by a hard reset. The slave registers are
clocked by CLK, and are readable and cleared by either a
hard or soft reset. The transfer of configuration data from the
master register to the slave register occurs synchronously
after an event and requires a four clock synchronization
period.
The μ P can perform back-to-back accesses to the register,
but must maintain four f CLK periods between accesses to
the same address. This limits the maximum μ P access rate
for the RAM to 125MHz/4 = 31.25MHz.
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